The present invention relates generally to integrated circuits. More particularly, the invention relates to reducing leakage current in integrated circuits.
Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory to store information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.
FIG. 1 shows a conventional SRAM cell 101. The SRAM cell comprises first and second transistors 110 and 120 coupled to a latch 130, which stores a bit of information. One transistor is coupled to a bit line 140 and the other is coupled to a bit line complement 141 while the gates are coupled to a word line 135. The latch includes first and second inverters 133 and 134, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime. In order to restore the information stored in the cell, a refresh operation is required. Typically, refreshing of memory cells interrupt the normal operation, adversely impacting performance.
As evidenced from the above discussion, it is desirable to provide a memory cell with reduced leakage current in order to improve retention time.
The present invention relates generally to memory cells. More particularly, the invention relates to improving retention time in memory cells. In one embodiment, the memory cell comprises first and second access transistors coupled to respective first and second terminals of a storage transistor. Bit lines are coupled to first terminals of the access transistors and word lines are coupled to the gates of the access transistors. In one embodiment, a degraded logic 0 is written to the memory cell during a write 0, causing the memory cell to store a degraded logic 0. Storing a degraded logic 0 in the memory cell reduces leakage current.